In semiconductor technology, an integrated circuit pattern can be defined on a substrate using a photolithography process. Dual damascene processes are utilized to form multilayer copper interconnections including vertical interconnection vias and horizontal interconnection metal lines. During a dual damascene process, a plug filling material is employed to fill in the vias and the material is then etched back. However, the etch-back process has a relatively high manufacturing cost.
After the plug filling material has been filled and etched back, a lithography patterning process is performed. Typically, a photoresist layer is coated on the substrate for the patterning process. The photoresist layer can have significant variances in thickness and reflectivity, which degrades controls on exposure depth and critical dimension (CD) of the photoresist. This, in turn, adversely affects the lithography patterning process.